1. Field of the Invention
This invention relates to Phase Shift Key (PSK) receivers or demodulators. More particularly, the present invention relates to a new and improved receiver having its automatic gain control (AGC) circuit A.C. coupled to the base band stages of the phase lock loop (PLL) to provide an improved signal to noise ratio (SNR) data output.
2. Description of the Prior Art
Heretofore, PLL circuits for receivers and AGC circuits for PLLs were known. However, the prior art AGC circuits had their voltage control gain devices coupled to the intermediate frequency (IF) stage where the noise and interference signals, such as jamming signals are amplified before entering the PLL.
It has been suggested that the prior art detector in the data branch of the phase lock loop be placed after the low pass filter in the data branch of the phase lock loop and the detector output be coupled back to the input of the AGC loop filter. When this is done, the output of the AGC loop filter is still coupled back to the voltage control gain device in the IF stage where the noise and the interference signals are still amplified before entering the phase lock loop.
It would be extremely desirable to provide a PSK receiver that minimizes the noise amplification in the automatic gain control circuit and thus provides an improved signal to noise ratio of the data output signals during both acquisition and after lock on.